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The design of a differential CMOS charge pump for high performance phase-locked loops

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2 Author(s)
B. Terlemez ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; J. P. Uyemura

The design methodology and the test results of a low-voltage differential charge pump structure for phase-locked loop (PLL) applications are presented. The structure is composed of two charge/discharge blocks, a replica bias circuit, and a sampled data common-mode feedback (CMFB) block that adjusts the pump-up current for symmetrical differential outputs and a wider output voltage range. A prototype is fabricated using a 0.18 μm n-well CMOS technology to test the charge pump in a high performance PLL, running internally at 2.5 GHz with -123 dBc/Hz phase noise at 1 MHz frequency offset.

Published in:

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on  (Volume:4 )

Date of Conference:

23-26 May 2004