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A novel 1.5 V CMFB CMOS down-conversion mixer design for IEEE 802.11 A WLAN systems

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3 Author(s)
Xuezhen Wang ; Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA ; R. Weber ; Degang Chen

This paper presents a 5.8 GHz low voltage down-conversion mixer design integrated in a TSMC 0.18 μm CMOS process. The proposed method features that an RF input stage converts the RF input voltage to current, which is coupled to the core of Gilbert Cell using current mirror. This implementation eliminates the current source transistor at bottom and furthermore reduces the supply voltage. Common-mode feedback is used for the active load of the mixer. The LO frequency is at 5.6 GHz. The designed mixer requires only a 1.5 V supply voltage and consumes 11.78 mW DC power. At 5.8 GHz, this mixer has single-sideband noise figure (SSB NF) of 13.6 dB, with input return loss of -18 dB, with output return loss of -26.4 dB, Third-order Input Intercept Point (IIP3) of -10.66 dBm, and conversion gain of 10.4 dB.

Published in:

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on  (Volume:4 )

Date of Conference:

23-26 May 2004