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A 1/8-rate clock and data recovery architecture for high-speed communication systems

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2 Author(s)
Sameni, P. ; Dept. of Electr. & Comput. Eng., British Columbia Univ., Vancouver, BC, Canada ; Mirabbasi, S.

A new clock and data recovery (CDR) architecture for high-speed communication applications is introduced. The proposed CDR architecture is described in the context of a 40-Gb/s optical communication system. This architecture utilizes 1/8-rate clock to recover and demultiplex the data, and it does not require a frequency divider. Also, the CDR system employs a rate-reduction block to lower the data transition density and thereby alleviates the speed requirements of the data recovery process. For a 40-Gb/s system, the CDR uses a multiphase voltage-controlled oscillator (VCO) with 5-GHz center frequency. The proposed architecture is particularly suitable for deep submicron CMOS designs where the designer encounters difficulties in implementing a full-rate clock and data recovery.

Published in:

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on  (Volume:4 )

Date of Conference:

23-26 May 2004

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