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A 5-Gb/s clock and data recovery (CDR) circuit, incorporating 625 MHz interpolating voltage-controlled oscillators (VCO) and four-phase 1/8-rate phase detectors (PD), is demonstrated. The PD provides a linear characteristic that is proportional to the phase difference between the four-phase clocks and the input 5-Gb/s data, and hence produces four-demultiplexed 1.25-Gb/s outputs. The VCO is designed as a four-stage differential ring oscillator, employing the half-rate clock technique so that it can provide 1/8-rate clocks with delay interpolation. Test chips are fabricated in a 0.25 μm CMOS technology. The whole chip occupies an area of 1.7×1.4 mm2 together with on-chip low pass filters, i.e., two 16 pF capacitors and 63 kΩ resistors. Post-layout simulations show that the recovered data output exhibits 40psp-p jitter characteristic for 223-1 PRBS serial NRZ input. The chip core dissipates 130 mW from a single 2.5 V supply.