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A 5.1-GHz CMOS PLL based integer-N frequency synthesizer with ripple-free control voltage and improved acquisition time

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2 Author(s)
S. Ali ; Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA ; M. Margala

A 5.1-GHz integer-N CMOS phase locked loop (PLL) based frequency synthesizer is presented. A current mirror current source is used in designing the charge pump loop filter. A completely ripple-free VCO input control voltage is achieved using new mirror architecture in the charge pump loop filter. The acquisition time is improved by a factor of 1.62 using a new design methodology. The synthesizer operates from 4.92 to 5.1-GHz and achieves a phase noise of -121.9 dBc/Hz at 10-MHz offset frequency from the carrier for maximum oscillation frequency. The output rms jitter is 0.3% of the oscillator period. The total power consumption of this synthesizer is 10-mW. The PLL is designed and extracted in TSMC 0.18-μm technology for GSM applications.

Published in:

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on  (Volume:4 )

Date of Conference:

23-26 May 2004