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A low-power, hard-decision analogue convolutional decoder using the modified feedback decoding algorithm

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2 Author(s)
Tomatsopoulos, B. ; Dept. of Electron. & Electr. Eng., Univ. Coll. London, UK ; Demosthenous, A.

This paper describes the design of a constraint length 3, rate-1/2, hard-decision convolutional decoder using the modified feedback decoding algorithm (MFDA). The decoder employs mostly analogue current-mode circuits and is optimized for low-power dissipation at the expense of operating speed. This is important in many portable applications where trading size and power dissipation against operating speed is desired. Post-layout simulations using a 0.8 μm CMOS technology indicate that the decoder can operate at data rates of about 2.5 Mbit/s and dissipates only 3.9 mW from a single 3 V power supply. The layout core area is about 1 mm2.

Published in:

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on  (Volume:4 )

Date of Conference:

23-26 May 2004

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