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Two low power flexible Rake receiver architectures are presented. The first architecture exploits the statistical distribution of multipath delays in wireless channels to reduce power dissipation. The second Rake architecture is based on a tradeoff between algorithm accuracy and circuit complexity. By introducing a negligible performance degradation, the SRAM memory for the input sample buffer is eliminated, achieving low power consumption and small silicon area. Both Rake architectures are targeted for third generation WCDMA mobile terminals (downlink receivers), but the circuits can also be applied to base station (uplink) receivers. The architectures have been synthesized in a 0.18 μm standard cell CMOS technology using Cadence BuildGates. The proposed architectures achieve significant area and power savings as compared to previous circuits described in the literature.