By Topic

A low-power fractional decimator architecture for an IF-sampling dual-mode receiver

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Uusikartano, R. ; Inst. of Digital & Comput. Syst., Tampere Univ. of Technol., Finland ; Takala, J.

In this paper, a low-power fractional decimator architecture for a GSM/WCDMA dual-mode receiver is presented. The decimation by a fractional ratio is performed using a cascaded integrator-comb filter with three parallel derivator branches, and a linear interpolator. In the proposed design, all the integrators are clocked at half the sample rate, which is possible by utilizing the zero samples produced in the downconversion. Although the presented architecture has a larger layout area than the traditional designs, this maximum clock frequency reduction yields lower power consumption and, depending on the implementation technology and parameters, a possibility to use more power- and area-efficient adders in the speed-critical integrator section.

Published in:

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on  (Volume:3 )

Date of Conference:

23-26 May 2004