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Design issues and performance limitations of a clock jitter insensitive multibit DAC architecture for high-performance low-power CT ΣΔ modulators

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3 Author(s)
Gerfers, F. ; BL Display Process., Phillips Semicond., Starnberg, Germany ; Ortmanns, M. ; Manoli, Y.

This paper covers a general design guidelines, implementation issues as well as performance limitations of a clock-jitter insensitive multibit digital-to-analog converter (DAC) topology for high-performance low-power continuous-time ΣΔ modulators. Since, the considered DAC building block uses a time-variant feedback pulse shape both the clock jitter influence as well as the slew rate and bandwidth requirements of the used amplifiers are reduced so that also the overall power consumption of the modulator is decreased. It will be shown that the proposed concept provides various benefits over the commonly used current-source DACs. Additionally, the influence of a number of circuit non-idealities is analytically determined and verified by behavioural simulations in order to minimize their impact on the modulator performance on the one hand and to optimize the overall power consumption on the other hand. In particular, the effects of clock jitter, random device mismatch, finite switch resistance, circuit noise as well as the limited output impedance is analyzed. Besides, the impact of amplifier confinements like finite DC-gain as well as gain-bandwidth are evaluated.

Published in:

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on  (Volume:1 )

Date of Conference:

23-26 May 2004