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A pipelined ADC architecture that exhibits both power and area efficiencies is proposed to be accountable for the major baseband functions of the recently introduced two-step-channel-select (2-SCS) low-IF receiver. Such architecture comprises: 1) a sample and hold (S/H) front-end implementing analog-double quadrature sampling (A-DQS) for IF-to-baseband downconversion and IF channel selection; and 2) one OTA-shared pipeline ADC is employed for digitalization both I and Q channels through I/Q-multiplexing. An IC prototype was designed in a 0.35μm CMOS process with 20-MS/s 8-bit resolution, which has been targeted for 2.4-GHz ISM band standards. The key simulated performances achieved 7.7-b ENOB with INL and DNL within ±0.5 LSB and ±0.34 LSB, respectively. A competitive chip area of only 1.34 mm2 is achieved, while dissipating an average of 54.5 mW from 2.5 V.
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on (Volume:1 )
Date of Conference: 23-26 May 2004