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We present a new pseudo-differential comparator block that behaves like a comparator array, but has a reduced area, power consumption, and input capacitance. By combining two of the new comparator blocks with input sample and hold circuits, in an interleaving architecture, and by using a Wallace-tree encoder, it is possible to obtain an ADC with limited resolution (up to 6 bits), but with very low power consumption, and also with low area and low supply voltage. As an example, we have designed 4-bit ADC as a coarse converter in a 13 bit pipeline ADC. . It is implemented in a 0.35μm CMOS technology, has 0.034mm2 and has power consumption of 210 μW, with an estimated input capacitance of 11 fF.
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on (Volume:1 )
Date of Conference: 23-26 May 2004