RF CMOS fully-integrated heterodyne front-end receivers design technique for 5 GHz applications

This paper presents an architecture that allows the implementation of fully integrated heterodyne 5GHz RF receivers. The front-end circuitry consists of a low noise amplifier, a critical cascade of two notch filters, an active mixer, and a voltage controlled oscillator. The notch filters, which use on chip inductor Q-factor enhancement techniques, are designed to provide a wide bandwidth of image rejection (IR), eliminating the need for accurate IR tuning circuitry. More than 40dB of image rejection can be obtained in a standard 0.18μm CMOS technology, for a 400MHz bandwidth centered at 7.2GHz, without having to resort to the overhead and the complexity of automatic tuning circuits. Design issues of homodyne and heterodyne 5GHz front-end receivers are received and discussed.