By Topic

Testing high resolution ADCs using deterministic dynamic element matching

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Olleta, B. ; Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA ; Hanjun Jiang ; Degang Chen ; Geiger, R.

Dynamic element matching (DEM) is an effective approach to achieving good average performance in the presence of major mismatch in matching-critical circuits. This paper presents a deterministic DEM (DDEM) strategy for ADC testing that offers substantial reductions in testing cost. The approach is mathematically formulated and validated with simulation results that show the number of test vectors needed is comparable to what are concurrently used with standard code density linearity testing. It is demonstrated that the DDEM method can be used to accurately test ADCs with linearity that far exceeds that of the DAC used as a signal generator. This technique offers potential for use in both production test and BIST environments where high linearity devices are difficult to test and characterize.

Published in:

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on  (Volume:1 )

Date of Conference:

23-26 May 2004