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This work presents a low-voltage CMOS amplifier. The amplifier combines a p-channel differential input pair and a level-shift p-channel differential input pair to obtain rail-to-rail signaling. Simulations using a 0.35 μm 2p4m CMOS process at 1 V supply voltage, the amplifier performs 76 dB dc gain, 5.27 MHz unit-gain bandwidth, 288 μW power dissipation and 84° phase margin at 15 pF output load.
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on (Volume:1 )
Date of Conference: 23-26 May 2004