A low-voltage CMOS rail-to-rail operational amplifier using double p-channel differential input pairs

This work presents a low-voltage CMOS amplifier. The amplifier combines a p-channel differential input pair and a level-shift p-channel differential input pair to obtain rail-to-rail signaling. Simulations using a 0.35 /spl mu/m 2p4m CMOS process at 1 V supply voltage, the amplifier performs 76 dB dc gain, 5.27 MHz unit-gain bandwidth, 288 /spl mu/W power dissipation and 84/spl deg/ phase margin at 15 pF output load.