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This paper presents the design of a third-order low-pass ΣΔ analog-to-digital converter (ADC) employing a continuous-time (CT) loop filter. The loop filter is implemented using Gm - C integrators, where the transconductors are implemented using CMOS transistors only. System level as well as transistor level design issues for power efficiency is discussed. A prototype ΣΔ ADC intended for weak biological signals restricted to bandwidths below 4 kHz has been manufactured in a standard 0.35 μm CMOS technology. The ADC has a measured resolution of 10 bits and a dynamic range (DR) of 67 dB at a sampling rate of fs = 1.4 MHz, while drawing a bias current of 60 μA from a modest supply voltage of 1.8 V, thus consuming 108 μW of power.
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on (Volume:1 )
Date of Conference: 23-26 May 2004