By Topic

A CMOS low-power ADC for DVB-T and DVB-H systems

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Adeniran, O.A. ; Sony Semicond. & Electron. Solutions, Hampshire, UK ; Demosthenous, A. ; Clifton, C. ; Atungsiri, S.
more authors

This paper describes the design of a 10-bit, 25MS/s analogue-to-digital converter (ADC) suitable for digital video broadcasting over terrestrial (DVB-T) and handheld (DVB-H) systems. The ADC is based on a 4-3-3-stage pipeline architecture and employs dynamic comparators and Miller-hold sample-and-hold amplifiers for high-speed operation and low-power consumption. Simulated results in a 0.35μm CMOS process show that the converter achieves 56dB signal-to-noise ratio(SNR) and 57dB spurious-free dynamic range (SFDR). The converter input range is 2V peak-to-peak differential and the total power consumption is 27mW from a 2.8V power supply.

Published in:

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on  (Volume:1 )

Date of Conference:

23-26 May 2004