By Topic

Design and characterisation of pseudo-DTL CMOS gates

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Grigoleit, M. ; Simon Fraser Univ., Sch. of Eng. Sci., Burnaby, BC, Canada ; Syrzycki, M.

A novel approach to CMOS logic gate design, using elements of diode-transistor logic (DTL), has been applied to multiple-input NAND gates. The resulting circuits have been compared with equivalent static CMOS designs, and are shown to offer several advantages.

Published in:

Electronics Letters  (Volume:27 ,  Issue: 17 )