A 12-bit 40MSPS 3.3-V 56-mW pipelined A/D convereter in 0.25-/spl mu/m CMOS [convereter read converter]

In this paper, a very low-power high-speed high-resolution pipelined analog-to-digital converter (ADC) based on an optimization methodology previously proposed by the authors, is presented. By expressing the total static power consumption and the total input-referred noise of the converter as function of the capacitor values and the resolutions of the converter stages, a simple optimization algorithm is employed to calculate the optimum values of these parameters, which lead to minimum power consumption while a specified noise requirement is satisfied. Design considerations and simulation results of the 12-bit 3.3V 40MS/s pipelined ADC with only 56mW consumption in a 0.25/spl mu/m CMOS process, are presented. The simulated values of the SNR and SFDR are 69dB and 75dB respectively.