Referenced Items are not available for this document.
A large-signal piecewise-linear model is proposed for bang-bang phase detectors that predicts characteristics of clock and data recovery circuits such as jitter transfer, jitter tolerance, and jitter generation. The results are validated by 1-Gb/s and 10-Gb/s CMOS prototypes using an Alexander phase detector and an LC oscillator.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:39
,
Issue:
9
)
Date of Publication: Sept. 2004
- Page(s):
- 1571 - 1580
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 8113045
- Digital Object Identifier :
- 10.1109/JSSC.2004.831600
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 30 August 2004
- Issue Date :
- Sept. 2004
- Sponsored by :
- IEEE Solid-State Circuits Society
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
