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Analysis and modeling of bang-bang clock and data recovery circuits

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3 Author(s)
Jri Lee ; Dept. of Electr. Eng., Univ. of California, Los Angeles, CA, USA ; Kundert, K.S. ; Razavi, B.

A large-signal piecewise-linear model is proposed for bang-bang phase detectors that predicts characteristics of clock and data recovery circuits such as jitter transfer, jitter tolerance, and jitter generation. The results are validated by 1-Gb/s and 10-Gb/s CMOS prototypes using an Alexander phase detector and an LC oscillator.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:39 ,  Issue: 9 )