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A novel erase scheme to suppress overerasure in a scaled 2-bit nitride storage flash memory cell

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10 Author(s)
Chih-Chieh Yeh ; Macronix Int. Co. Ltd., Hsinchu, Taiwan ; Tahui Wang ; Wen-Jer Tsai ; Chih-Yuan Lu
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The cause of over-erasure in a two-bit nitride storage flash memory cell is investigated. Extra positive charges accumulated above the n+ junction and channel-shortening enhanced drain-induced barrier lowering effect are found to be responsible for threshold voltage (Vt) lowering in an over-erased cell. A modified erase scheme is proposed to resolve this issue. By applying a source voltage during erase, the erase speed can be well controlled for cells with different channel lengths and a wide range of program-state Vt distribution, which will reduce overerasure significantly.

Published in:

Electron Device Letters, IEEE  (Volume:25 ,  Issue: 9 )