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Cached memory performance characterization of a wireless digital baseband processor

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3 Author(s)
S. Kannaw ; Analog Devices Inc, Austin, TX, USA ; M. Allen ; J. Fridman

We present performance analysis results of the MSP500 digital baseband (DBB) platform, a system developed at Analog Devices Inc., targeted at cellular handsets supporting the GSM, GPRS, and EDGE communication standards. We focus on a particular member of the MSP500 family, the AD6532 device, which integrates a Blackfin® core, and examine the execution time performance of a number of wireless physical layer software components from the perspective of an instruction- and data-cached memory hierarchy. The Blackfin is a 16-bit fixed-point core that combines some of the best features of DSPs and micro-controllers, and has support for a cached memory system.

Published in:

Acoustics, Speech, and Signal Processing, 2004. Proceedings. (ICASSP '04). IEEE International Conference on  (Volume:5 )

Date of Conference:

17-21 May 2004