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In this paper, we propose a flexible architecture that performs the computation of the discrete wavelet transform, requiring a small memory space and is capable of operating at high sampling rate. The architecture employs two filtering blocks to compute the transform and one buffer to store the intermediate results. Each filtering block has two processing units that operate independently in parallel using a two-phase scheduling. An efficient scheme for the synchronization of the data flow among the three blocks is provided in order to minimize the buffer size and increase the speed of operation. Verilog and HSPICE simulation results are presented to show that the proposed architecture is more efficient for the computation of a fully decomposed discrete wavelet transform with high-tap filters than some other existing architectures in terms of their areas and speed of operations.