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A novel high performance distributed arithmetic adaptive filter implementation on an FPGA

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5 Author(s)
Allred, D.J. ; Center for Signal & Image Process., Georgia Inst. of Technol., Atlanta, GA, USA ; Yoo, Heejong ; Krishnan, V. ; Huang, W.
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In this paper, an FIR adaptive filter implementation, using a multiplier-free architecture, is presented. The implementation is based on distributed arithmetic (DA) which substitutes multiply-and-accumulate operations with a series of look-up-table (LUT) accesses. This can be achieved at the cost of a moderate increase in memory usage. The proposed design performs an LMS-type adaptation on a sample-by-sample basis. This is accomplished by an innovative LUT update using a matched auxiliary LUT. The system is implemented on an FPGA that enables rapid prototyping of digital circuits. Implementation results are provided to demonstrate that a high-speed, low logic complexity LMS adaptive filter can be realized employing the proposed architecture.

Published in:

Acoustics, Speech, and Signal Processing, 2004. Proceedings. (ICASSP '04). IEEE International Conference on  (Volume:5 )

Date of Conference:

17-21 May 2004