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Area efficient decoding of quasi-cyclic low density parity check codes

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3 Author(s)
Zhongfeng Wang ; Sch. of Electr. Eng., & Comput. Sci., Oregon State Univ., Corvallis, OR, USA ; Chen, Yanni ; Parhi, K.K.

This paper exploits the similarity between the two stages of belief propagation decoding algorithm for low density parity check codes to derive an area efficient design that re-maps the check node functional units and variable node functional units into the same hardware. Consequently, the novel approach could reduce the logic core size by approximately 21% without any performance degradation. In addition, the proposed approach improves the hardware utilization efficiency as well.

Published in:

Acoustics, Speech, and Signal Processing, 2004. Proceedings. (ICASSP '04). IEEE International Conference on  (Volume:5 )

Date of Conference:

17-21 May 2004