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A low power reconfigurable DCT architecture to trade off image quality for computational complexity

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2 Author(s)
Jongsun Park ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; Roy, K.

We present a low power reconfigurable DCT design, which achieves considerable computational complexity reduction in DCT operation with minimum image quality degradation. The approach is based on the modification of DCT bases in a bit-wise manner. Different computational complexity/image quality trade off levels are presented and a reconfigurable architecture. which can dynamically change from one trade off level to another, is also proposed. The reconfigurable DCT architecture can achieve power savings ranging from 20% to 70% for 5 different trade off levels.

Published in:

Acoustics, Speech, and Signal Processing, 2004. Proceedings. (ICASSP '04). IEEE International Conference on  (Volume:5 )

Date of Conference:

17-21 May 2004