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Investigation and modeling of interface and bulk trap generation during negative bias temperature instability of p-MOSFETs

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3 Author(s)
S. Mahapatra ; Dept. of Electr. Eng., Indian Inst. of Technol. Mumbai, India ; P. B. Kumar ; M. A. Alam

Negative bias temperature instability is studied in thick and thin gate oxide p-MOSFETs. The relative contributions of interface- and bulk-trap generation to this device degradation mode are analyzed for a wide range of stress bias and stress temperature. The effects of gate voltage and oxide field, as well as those of inversion layer holes, impact ionized hot holes, and hot electrons on interface- and bulk-trap generation, are identified. The bulk-trap generation process is interpreted within the modified anode-hole injection model and the mechanism of interface-trap generation is modeled within the framework of the classical reaction-diffusion theory. The diffusion species for interface-trap generation is unambiguously identified. Moreover, a high-temperature, diffusion-triggered, enhanced interface-trap generation mechanism is discussed for thin gate oxide p-MOSFETs. Finally, a novel scaling methodology is proposed for interface-trap generation that helps in obtaining a simple, analytical model useful for reliability projection.

Published in:

IEEE Transactions on Electron Devices  (Volume:51 ,  Issue: 9 )