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A high throughput, reconfigurable field programmable gate array (FPGA) implementation of the soft output Viterbi algorithm (SOVA) is described. Such a SOVA module provides the soft information needed by an iterative soft decoder used with Turbo codes and low density parity check (LDPC) codes. The implementation of the SOVA algorithm runs at 100 Mb/s on Xilinx Virtex II 2000 FPGA. Using a higher capacity FPGA and repeating the circuit doubles the throughput. The design can be reconfigured for different partial response (PR) targets. The design requires about 5 kb of memory for the EPR4 channel and may be integrated on a single chip with serially implemented LDPC decoder.