A GA-based design space exploration framework for parameterized system-on-a-chip platforms

The constant increase in levels of integration and reduction in the time-to-market has led to the definition of new methodologies, which lay emphasis on reuse. One emerging approach in this context is platform-based design. The basic idea is to avoid designing a chip from scratch. Some portions of the chip's architecture are predefined for a specific type of application. This implies that the basic micro-architecture of the implementation is essentially "fixed," i.e., the principal components should remain the same within a certain degree of parameterization. Many researchers predict that platforms will take the lion's share of the integrated circuit market. In this paper, we propose an approach based on genetic algorithms for exploring the design space of parameterized system-on-a-chip (SOC) platforms. Our strategy focuses on exploration of the architectural parameters of the processor, memory subsystem and bus, making up the hardware kernel of a parameterized SOC platform for the design of embedded systems with strict power consumption and performance constraints. The approach has been validated on two different parameterized architectures: one based on a RISC processor and another based on a parameterized very long instruction word architecture. The results obtained on a suite of benchmarks for embedded applications are discussed in terms of both accuracy and efficiency. As far as accuracy is concerned, the approach gives solutions uniformly distributed in a region less than 1% from the Pareto-optimal front. As regards efficiency, the exploration times required by the approach are up to 20 times shorter than those required by one of the most efficient and widely referenced approaches in the literature.