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Queue processor architecture for novel queue computing paradigm based on produced order scheme

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5 Author(s)
Abderazek, B.A. ; Graduate Sch. of Inf. Syst., Electro-Commun. Univ., Tokyo, Japan ; Arsenji, M. ; Shigeta, S. ; Yoshinaga, T.
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This work proposes a novel produced order parallel queue processor architecture. To store intermediate results, the proposed system uses a FIFO queue registers instead of random access registers. Datum is inserted in the queue in produced order scheme and can be reused. We show that this feature has a profound implication in the areas of parallel execution, programs compactness, hardware simplicity and high execution speed. Our preliminary performance evaluations have shown a significant performance improvement (e.g., 10% to 26% decrease in program size and 6% to 46% decrease in execution time over a range of benchmark programs) when compared with the earlier proposed architecture.

Published in:

High Performance Computing and Grid in Asia Pacific Region, 2004. Proceedings. Seventh International Conference on

Date of Conference:

20-22 July 2004