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A new front-end chip (FE-I2) has been developed for the ATLAS pixel detector at the future Large Hadron Collider (LHC) accelerator facility of the European Laboratory for Particle Physics (CERN). This chip has been submitted in a commercial 0.25-μm CMOS process using special layout techniques for radiation tolerance. It comprises 2880 pixels arranged into 18 columns of 160 channels. Each pixel element of dimension 50 μm × 400 μm is composed of a charge- sensitive amplifier followed by a fast discriminator with a detection threshold adjustable within a range of 0-6000 electrons and slow control logic incorporating a wired-hit-Or, preamplifier-kill, readout mask, and automatic threshold tuning circuitry. There are two single-event-upset (SEU)-tolerant DACs for reducing threshold (7-b) and recovery-time (3-b) mismatches from pixel to pixel along with digital hit emulation and a differential readout circuit aimed at transporting time-stamped data from each pixel to buffers at the bottom of the chip. In comparison to previous generations of the ATLAS pixel chip, FE-I2 incorporates many new features such as embedded "smart" decoupling capacitances, long-term overvoltage protection, linear regulators, a capacitance calibration charge-pump circuit, a power-on reset, and a leakage current monitoring circuit. Its predecessor (FE-I1) has been demonstrated to operate correctly after ionizing radiation doses exceeding 50 Mrad (SiO2). Special techniques employed for digital pick-up reduction are also described.