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Interconnect energy dissipation in high-speed ULSI circuits

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3 Author(s)
Heydari, P. ; Dept. of Electr. & Comput. Eng., Univ. of California, Irvine, CA, USA ; Abbaspour, S. ; Pedram, M.

This paper presents a detailed empirical study and analytical derivation of voltage waveform and energy dissipation of global lines driven by CMOS drivers. It is shown that at high clock frequencies where the output voltage at the termination point of the transmission line may not reach its steady-state value during the clock period, it is possible to reduce energy dissipation while meeting a dc noise margin by driver sizing. This is in sharp contrast with the steady-state analysis, which states that driver size has no impact on the energy dissipation per output change. In addition, we propose a new design metric which is the product of energy, delay and some measure of ringing in lossy transmission lines. In particular, this paper provides closed-form expressions for the energy dissipation, 50% propagation delay, and the percentage of maximum undershoot when the circuit exhibits an underdamped behavior. This metric is used during the driver sizing problem formulation for minimum energy-delay-ringing product. The experimental results carried out by HSPICE simulation verify the accuracy of our models.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:51 ,  Issue: 8 )

Date of Publication:

Aug. 2004

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