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Hardware efficient fast parallel FIR filter structures based on iterated short convolution

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2 Author(s)
Chao Cheng ; VIA Technol. (China) Inc. Ltd., Beijing, China ; Parhi, K.K.

This paper presents an iterated short convolution (ISC) algorithm, based on the mixed radix algorithm and fast convolution algorithm. This ISC-based linear convolution structure is transposed to obtain a new hardware efficient fast parallel finite-impulse response (FIR) filter structure, which saves a large amount of hardware cost, especially when the length of the FIR filter is large. For example, for a 576-tap filter, the proposed structure saves 17% to 42% of the multiplications, 17% to 44% of the delay elements, and 3% to 27% of the additions, of those of prior fast parallel structures, when the level of parallelism varies from 6 to 72. Their regular structures also facilitate automatic hardware implementation of parallel FIR filters.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:51 ,  Issue: 8 )