By Topic

Extending the transaction level modeling approach for fast communication architecture exploration

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Pasricha, S. ; University of California, Irvine, CA ; Nikil Dutt ; Ben-Romdhane, M.

System-on-chip (SoC) designs are increasingly becoming more complex. Efficient on chip communication architectures are critical for achieving desired performance in these systems. System designers typically use Bus Cycle Accurate (BCA) models written in high level languages such as C/C++ to explore the communication design space. These models capture all of the bus signals and strictly maintain cycle accuracy, which is useful for reliable performance exploration but results in slow simulation speeds for complex designs, even when they are modeled using high level languages. Recently there have been several efforts to use the Transaction Level Modeling (TLM) paradigm for improving simulation performance of BCA models. However these BCA models capture a lot of details that can be eliminated when exploring communications architectures.

Published in:

Design Automation Conference, 2004. Proceedings. 41st

Date of Conference:

7-11 July 2004