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CMOS implementation of programmable logic gates and pipelined full adders using threshold logic gates based on NDR devices

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3 Author(s)
Mira, R. ; Dept. of Electr. Eng., Alexandria Univ., Egypt ; El-Sayed, Mohamed ; El-Faramawy, N.

This paper presents a new prototyping technique, which allows efficient verification of circuit concepts based on negative differential resistance (NDR) devices. This prototype, which is called MOS-NDR, has been used to implement programmable logic gates and pipelined-ripple-carry full adders using linear threshold gates (LTGs).

Published in:
Radio Science Conference, 2004. NRSC 2004. Proceedings of the Twenty-First National

Date of Conference: 16-18 March 2004

Page(s):
D3 - 1-8
Print ISBN:
977-5031-77-X
INSPEC Accession Number:
8168629
Digital Object Identifier :
10.1109/NRSC.2004.1321855
Product Type:
Conference Publications

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