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Optimizing manufacturability by design for yield

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1 Author(s)
Zorian, Y. ; Virage Logic Corp., Fremont, CA, USA

Today's semiconductor fabrication processes for nanometer technology allows the creation of a very high-density and high-speed system on chip (SoC). Unfortunately, this finer, denser and faster chip results in defect susceptibility levels that reduce process yield and reliability. This lengthens the production ramp-up period and hence affects profitability. The impact of nanometer technology on yield and reliability creates a dilemma for users of the conventional chip realization flow. Each chip realization phase affects manufacturing yield and field reliability. To optimize yield and reach reliability levels, the industry uses advanced optimization solutions, designed in and leveraged at different phases of the chip realization flow. Recognizing the importance of this topic, this paper is dedicated to design for yield and reliability solutions. The ability to achieve acceptable levels of yield and reliability is likely to worsen as SoCs move to more aggressive technologies. To help solve this challenge, it is important to first identify the potential sources of yield loss and understand the faults that result in reliability failures. In order to address the yield loss problem, a new type of IP block is called infrastructure IP. It is meant to ensure the manufacturability of the SOC and to achieve adequate levels of yield and reliability. The infrastructure IP leverages the manufacturing knowledge and feeds back the information into the design phase. This paper analyzes the key trends and challenges resulting in manufacturing susceptibility and field reliability that necessitate the use of such infrastructure IP. It also describes several examples of such embedded IPs for detection, analysis and correction.

Published in:

Electronics Manufacturing Technology Symposium, 2004. IEEE/CPMT/SEMI 29th International

Date of Conference:

July 14-16, 2004