By Topic

Development of novel packaging structures encapsulation process, materials and reliability for matrix array over-molded flip chip CSP

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

8 Author(s)
Kai-Chi Chen ; Mater. Res. Labs., Ind. Technol. Res. Inst., Osaka, Japan ; Hsun-Tien Li ; T. Nemoto ; Shu-Chen Huang
more authors

New technologies of structure, materials an encapsulating process for over-coated flip-chip chip scale package (OFCSP) have been developed in this study. A MAP (matrix array package) type flip chip package with over-coating is developed by simultaneous encapsulating process which has the same universal production system as mini-BGA and doesn't need to change molding facility due to die shrink or product changed. A 4×4 chips are array flip chip test vehicle was designed for this study. The new technology shows many advantages such as: high electric performance, low cost, good reliability property, high throughput, thinner package, and void free during encapsulating process. Not only remarkable down-sizing, but also a new developed package shows miraculous property of soldering resistance. OFSCP is developed by vacuum molding for simultaneous encapsulating process without void remain, and fine filler molding compounds for underfilling penetration well. According to failure analysis, internal stress on the die surface around solder bump will cause the package circuit-opened failure. OFCSP shows the smallest stress concentrated on the die surface from FEM (finite element model) analysis. It can pass perfectly pre-conditioned level 1 JEDEC standard at 230°C reflowing and level 2 JEDEC standard at 260°C reflowing. It can also pass the reliability testing items including USPCT, TCT and HST after pre-condition of JEDEC level 3. Since the perfect property of soldering resistance can be achieved by considering package structure, encapsulant properties and process, developed technology in this study can be applied for more advanced package such as paper-thin package, FC/WB embedded stacked package etc.

Published in:

Electronics Manufacturing Technology Symposium, 2004. IEEE/CPMT/SEMI 29th International

Date of Conference:

July 14-16, 2004