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Evaluation and simplified and complex thermal finite element models for 3-die stacked chip scale ball grid array package

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1 Author(s)
Zahn, B.A. ; Amkor Technol., Chandler, AZ, USA

Thermal performance testing was conducted on a 16×16mm, 2-metal layer, 591-ball, 0.50mm pitch, 1.20mm overall height chip scale package (CSP) containing an offset pyramid configuration of three stacked Delco thermal test die. Die sizes from bottom-to-top wee 10.16×10.16mm (Delco PST6), 6.35×6.35mm (Delco PST-4), and 3.817ties;3.81mm (Delco PST-2). Testing was carried out using eight different multi-die power configurations in a natural convection environment to highlight the effects of radiant and convective heat transfer. Measured data was obtained on a sample size of five packages to calculate Theta JA, Psi JT, and Psi JB values at each of the eight different multi-die power configurations. Furthermore, Theta JC and theta JB cold plate measurements were also obtained. For the purpose of thermal testing, each of the five CSP test samples were mounted on a JEDEC standard 101.5×1.60mm IS2P thermal test board. Measured results are used to suggest a methodology for the generation of linear superposition matrix equations as a means to present multi-die package thermal test data such that it may account for changes in thermal cross talk between die at varying die power configurations. The ANSYS finite element analysis modelling software was used to simulate the eight aforementioned thermal test configurations for the purpose of verifying the acquired test data. Both simplified and complex package substrate metal layer trace patterns were evaluated for simulation accuracy. The simplified patterns consisted of conductor traces that do not follow the detailed routing of the actual design, but instead extend straight outward towards the substrate edge. Alternatively, the complex patterns consisted of the detailed trace layers exactly as they are physically routed on the CSP susbtrate. In both the complex and simplified metal layer trace pattern finite element models, vias that connect the top and bottom trace layers were represented by two-dimensional thermal conduction elements. Simulated results for both the simplified and complex metal layer trace pattern models are compared to the acquired test data. The CSP package structure, thermal test data, and finite element models are presented and discussed.

Published in:

Electronics Manufacturing Technology Symposium, 2004. IEEE/CPMT/SEMI 29th International

Date of Conference:

July 14-16, 2004