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Gate poly-silicon critical dimension is one of the most important characteristics of up-to-date integrated circuit devices. Hence, in a semiconductor wafer fabrication process, gate poly-silicon critical dimension control is inevitable in order to achieve a competitive net-die-per-wafer yield as well as electrically acceptable device test characteristics. This paper presents a framework for statistical design of experiments and analysis on gate poly-silicon critical dimension. Three typical types of design of experiments are considered: 1) a nested design; 2) a randomized complete block design; and 3) a factorial design. With these designs, relevant linear statistical models are established. Based on the models, the analysis of variance technique and Duncan's multiple range tests are chosen as major methodologies not only to estimate related variance components but also to test uniformity on gate poly-silicon critical dimension. Statistical analyses are illustrated with experimental datasets from real pilot semiconductor wafer fabrication processes. Results show that: 1) according to the sources of variation, variance components are estimated separately, and 2) distinctive patterns of gate poly-silicon critical dimension can be detected with statistical significance. Consequently, the framework in this study can provide guidelines to practitioners on the variance components estimation as well as the uniformity test in parallel for any characteristic datasets collected from similar designs in a semiconductor wafer fabrication process.