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This paper illustrates how field programmable gate array (FPGA) is used as a process monitor for yield and performance improvements. Poly gate critical dimension (CD) variation has been increasingly affecting product performance and yield in advanced process technology. Here, a built-in-self-test (BIST) pattern-based poly gate CD measurement (Tilo) methodology is introduced in FPGA product. The FPGA circuit is programmed into a small, local BIST pattern (Tilo) and its delay is accurately reflecting local poly gate CDs and variation. This methodology can conveniently capture poly gate CD statistical variation at both the intrafield and interfield level. This paper shows that the Tilo measurement is very useful in poly process debugging and yield improvement.
Date of Publication: Aug. 2004