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An in-plane high-sensitivity, low-noise micro-g silicon accelerometer with CMOS readout circuitry

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3 Author(s)
Junseok Chae ; Dept. of Electr. Eng. & Comput. Sci., Univ. of Michigan, Ann Arbor, MI, USA ; Kulah, H. ; Najafi, K.

A high-sensitivity, low-noise in-plane (lateral) capacitive silicon microaccelerometer utilizing a combined surface and bulk micromachining technology is reported. The accelerometer utilizes a 0.5-mm-thick, 2.4×1.0 mm2 proof-mass and high aspect-ratio vertical polysilicon sensing electrodes fabricated using a trench refill process. The electrodes are separated from the proof-mass by a 1.1-μm sensing gap formed using a sacrificial oxide layer. The measured device sensitivity is 5.6 pF/g. A CMOS readout circuit utilizing a switched-capacitor front-end Σ-Δ modulator operating at 1 MHz with chopper stabilization and correlated double sampling technique, can resolve a capacitance of 10 aF over a dynamic range of 120 dB in a 1 Hz BW. The measured input referred noise floor of the accelerometer-CMOS interface circuit is 1.6μg/√Hz in atmosphere.

Published in:

Microelectromechanical Systems, Journal of  (Volume:13 ,  Issue: 4 )