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Algorithms for Taylor expansion diagrams [IC design/verification applications]

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3 Author(s)
Fey, G. ; Inst. of Comput. Sci., Bremen Univ., Germany ; Drechsler, R. ; Ciesielski, M.

The ever increasing size of integrated circuits results in large problem sizes during synthesis and verification of such designs. Recently Taylor expansion diagrams (TEDs) were introduced as a data structure to cope with large problem instances. TEDs allow us to exploit high level information in the representation of functions. In this paper, the basic TED operations are analyzed from a complexity point of view. Suggestions for optimizations of the originally proposed algorithms are made.

Published in:

Multiple-Valued Logic, 2004. Proceedings. 34th International Symposium on

Date of Conference:

19-22 May 2004