By Topic

A model for a reusable system-on-a-chip hardware component integrated with design exploration methodology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
A. M. Sllame ; Dept. of Comput. Sci., Al-Fateh Univ., Tripoli, Libya

This paper presents a proposal for reusable hardware core (component) model. The model is designed based on the knowledge gained by the exploiting the design space exploration methodology presented in (Sllame, 2003). The model structure contains component characterization, computation core specified in VHDL language, a test bench to smooth the component integration process within the application and interfacing.

Published in:

System-on-Chip for Real-Time Applications, 2004.Proceedings. 4th IEEE International Workshop on

Date of Conference:

19-21 July 2004