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Ultra low noise signed digit arithmetic using cellular neural networks

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3 Author(s)
Y. Ibrahim ; RCIM Res. Centre, Windsor Univ., Ont., Canada ; G. A. Jullien ; W. C. Miller

This paper addresses mixed-signal applications where the presence of digital switching noise is a major problem; for example, digital circuitry adjacent to sensitive bio-sensors in an SoC device. This paper describes a method for building ultra low-noise signed-digit arithmetic circuits using analog cellular neural networks, essentially implementing asynchronous digital logic with analog circuits. Each node in our asynchronous architectures uses controlled current sources driving into capacitors; providing both low current and voltage time derivatives (di/dt and dv/dt) and, as a result, reducing both instantaneous and average system and cross-talk noise. In this paper, we present the architecture of a signed-digit radix-2 adder with symmetrical digit set {-1,0,1}. The adder uses a new class of CNNs that has three stable states to match the three values of the digit set. The adder not only has all the known advantages of SD addition, but also greatly reduces switching noise. We also describe a 32x32-digit multiplier based on this technique. In a simulated comparison with CMOS digital counterparts in a 0.35μm CMOS technology, the peak system noise is 60-70dB lower for the CNN circuits.

Published in:

System-on-Chip for Real-Time Applications, 2004.Proceedings. 4th IEEE International Workshop on

Date of Conference:

19-21 July 2004