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Process parameter variations are expected to be significantly high in the sub-50 nm technology regime, which can severely affect the yield. In this paper, we analyze SRAM cell failure under process variation and propose a new fault tolerant cache architecture suitable for high performance applications. The faulty cells are dynamically detected and replaced by adaptively resizing the cache. The granularity of our resizing technique is low, and hence, the technique can handle a large number of faults. This scheme is transparent to processor architecture and has negligible energy and area overhead. This scheme also does not affect the cache access time and has minimum effect on processor performance. Experimental results on a 64 K cache, implemented using BPTM (Berkeley predictive technology model) 45 nm technology, show that using our technique, the effective yield can be increased to 94% from its original 33%.