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Concurrent error detection in sequential circuits implemented using FPGAs with embedded memory blocks

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1 Author(s)
Krasniewski, A. ; Inst. of Telecommun., Warsaw Univ. of Technol., Poland

We propose a low-overhead concurrent error detection scheme for a sequential circuit implemented using an FPGA with embedded memory blocks (EMBs). The presented scheme is proven to detect each permanent or transient fault associated with a single input or output of any component of the circuit that leads to an incorrect state transition. Such faults are detected with no latency. Our technique requires significantly less extra logic than the earlier proposed schemes for concurrent error detection in sequential circuits. For a large percentage of the examined benchmark circuits, no extra EMBs and just 3 extra LUTs are needed; for other circuits, the number of extra EMBs is quite limited - on average, an overhead in terms of the number of EMBs is 13.6%.

Published in:

On-Line Testing Symposium, 2004. IOLTS 2004. Proceedings. 10th IEEE International

Date of Conference:

12-14 July 2004