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IXP2400 network processor package development

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4 Author(s)
Janian, A. ; Intel Corp., Chandler, AZ, USA ; Hasan, A. ; Sheth, U. ; Barrett, A.

This paper describes the application and performance of network processors (NPU) and the development of packaging for the new IXP2400 NPUs. Flip chip interconnect packaging, applied first time to Intel NPUs, is described. The package used for very high I/O and ball count with a 1.0 mm pitch fully populated BGA is a first in its class. The details of the package substrate design are described and the package substrate characteristics along with validation are discussed. High ambient temperature for certain applications was specially challenging for cooling solutions. The techniques applied to circumvent packaging problems are described in the paper which include alignment of the package with the market demand and reconciling the silicon reliability for such solutions. The issues related to solder joint reliability for a 1.0 mm pitch BGA and its interactions with board level enabling are discussed with methods considered to improve it. Finally, the future direction of NPU products and the demands on packaging are listed.

Published in:

Electronic Components and Technology Conference, 2004. Proceedings. 54th  (Volume:1 )

Date of Conference:

1-4 June 2004

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