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Flip chip assembly experiments using small electroplated Au/Sn bumps, i.e. bumps of 50 μm in diameter and less, are carried out. After plating the bumps consist of a Au layer with a thinner Sn layer on top. Normally a reflow process in which the bumps are heated up to more than 280°C follows after which the bumps consist of a thick Au layer with an eutectic solder cap on top and a ζ-phase layer in between. However, the experiments prove that due to geometrical reasons as plated bumps rather than reflowed ones shall be used for bump sizes below 50 μm in diameter in order to achieve a high yield flip chip assembly process. Furthermore thermal cycling tests were carried out using flip chip assemblies consisting of a GaAs die soldered to a BCB thin film Silicon substrate. Assemblies with Au/Sn bumps of the size of 30 μm and 50 μm in diameter were tested this way.
Electronic Components and Technology Conference, 2004. Proceedings. 54th (Volume:1 )
Date of Conference: 1-4 June 2004