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The integration of more than a billion transistors on a chip, or gigascale integration (GSI), imposes significant constraints on interconnection and packaging of such chips. Specifically, the need for hundreds of amperes of dc current, very high input/output (I/O) bandwidth, high heat removal capability, and the interconnection of Si chips with low-k interlayer dielectric to boards with higher coefficient of thermal expansion (CTE) will challenge all aspects of conventional packaging and interconnection. A solution to the above described system level demands is the batch fabrication of high density and mechanically compliant electrical, optical, and thermal chip (I/O) interconnections at the wafer level. Such I/O interconnections are described in this paper.