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CMOS IC technology scaling and its impact on burn-in

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5 Author(s)
Vassighi, A. ; Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Ont., Canada ; Semenov, O. ; Sachdev, M. ; Keshavarzi, A.
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This article describes how CMOS IC technology scaling impacts semiconductor burn-in and burn-in procedures. Burn-in is a quality improvement procedure challenged by the high leakage currents that are rapidly increasing with IC technology scaling. These currents are expected to increase even more under the new burn-in environments leading to higher junction temperatures, possible thermal runaway, and yield loss of good parts during burn-in. The paper discusses the effect of junction temperature on device reliability, aging, and burn-in procedure optimization. The effect of device thermal runaway and the requirements it forces on commercial burn-in ovens, device package, and device cooling are also described.

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Device and Materials Reliability, IEEE Transactions on  (Volume:4 ,  Issue: 2 )