By Topic

Design optimization of AlInAs-GalnAs HEMTs for low-noise applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
J. Mateos ; Dept. de Fisica Aplicada, Univ. de Salamanca, Spain ; T. Gonzalez ; D. Pardo ; S. Bollaert
more authors

In order to optimize the low-noise performance of 50-nm-gate AlInAs-GalnAs high-electron mobility transistors (HEMTs), by using an ensemble Monte Carlo simulation we study the influence of three important technological parameters on their noise level: the doping of the δ-doped layer, the width of the devices and the length of the recess. The noise behavior of the devices is firstly analyzed in terms of the physics-based P, R, and C parameters, and then characterized from a practical (circuit oriented) point of view through their four noise parameters: minimum noise figure, Fmin, noise resistance, Rn, and complex input admittance, Yopt (or reflection coefficient, Γopt). We have observed an enhancement of the noise when the δ-doping or the device width are increased (a deterioration parallel to that of fmax). Thus, the optimum noise operation is obtained for the lowest possible values of the δ-doping and device width. However, for small width the effect of the offset parasitic capacitances makes Fmin increase, thus, imposing a limit for the reduction of the noise. Moreover, the increase of Rn for small W makes the noise tuning condition critical to reach the optimum low-noise operation. We have also confirmed that when shortening the recess length from 100 to 20 nm at each side of the gate Fmin is reduced, with a slight deterioration of fmax, while the static characteristics are not modified.

Published in:

IEEE Transactions on Electron Devices  (Volume:51 ,  Issue: 8 )