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Design optimization of AlInAs-GalnAs HEMTs for low-noise applications

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6 Author(s)
Mateos, J. ; Dept. de Fisica Aplicada, Univ. de Salamanca, Spain ; González, T. ; Pardo, Daniel ; Bollaert, S.
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In order to optimize the low-noise performance of 50-nm-gate AlInAs-GalnAs high-electron mobility transistors (HEMTs), by using an ensemble Monte Carlo simulation we study the influence of three important technological parameters on their noise level: the doping of the δ-doped layer, the width of the devices and the length of the recess. The noise behavior of the devices is firstly analyzed in terms of the physics-based P, R, and C parameters, and then characterized from a practical (circuit oriented) point of view through their four noise parameters: minimum noise figure, Fmin, noise resistance, Rn, and complex input admittance, Yopt (or reflection coefficient, Γopt). We have observed an enhancement of the noise when the δ-doping or the device width are increased (a deterioration parallel to that of fmax). Thus, the optimum noise operation is obtained for the lowest possible values of the δ-doping and device width. However, for small width the effect of the offset parasitic capacitances makes Fmin increase, thus, imposing a limit for the reduction of the noise. Moreover, the increase of Rn for small W makes the noise tuning condition critical to reach the optimum low-noise operation. We have also confirmed that when shortening the recess length from 100 to 20 nm at each side of the gate Fmin is reduced, with a slight deterioration of fmax, while the static characteristics are not modified.

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Electron Devices, IEEE Transactions on  (Volume:51 ,  Issue: 8 )